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TM
HM-6514/883
1024 x 4 CMOS RAM
Description
The HM-6514/883 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminates the need for pull up or pull down resistors. The HM-6514/883 is fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
March 1997
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Low Power Standby. . . . . . . . . . . . . . . . . . . 125W Max * Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max * Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min * TTL Compatible Input/Output * Common Data Input/Output * Three-State Output * Standard JEDEC Pinout * Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max * 18 Pin Package for High Density * Gated Inputs - No Pull Up or Pull Down Resistors Required * On-Chip Address Register
Ordering Information
120ns HM1-6514S/883 200ns HM1-6514B/883 300ns HM1-6514/883 TEMPERATURE RANGE -55oC to 125oC PACKAGE CERDIP PKG. NO. F18.3
Pinout
HM-6514/883 (CERDIP) TOP VIEW
A6 A5 A4 A3 A0 A1 A2 E GND 1 2 3 4 5 6 7 8 9 18 VCC 17 A7 16 A8 15 A9 14 DQ0 13 DQ1 12 DQ2 11 DQ3 10 W
PIN A E W D Q
DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
FN2996.1
151
HM-6514/883 Functional Diagram
LSB A9 A8 A7 A6 A5 A4 A LATCHED ADDRESS REGISTER A 6 GATED ROW DECODER 64 x 64 MATRIX
64
6 L L G A LATCHED ADDRESS REGISTER 4 A 4 G 4 1 OF 4 GATED COLUMN I/O SELECT 16 16 16 16
LSB A2 A1 A0 A3
E W DQ
152
HM-6514/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. HM-6514/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER Output Low Voltage SYMBOL VOL (NOTE 1) CONDITIONS VCC = 4.5V IOL = 3.2mA VCC = 4.5V IOH = -1.0mA VCC = 5.5V, VI = GND or VCC VCC = 5.5 V, VIO = GND or VCC VCC = 2.0V, E = VCC -0.3V, IO = 0mA VCC = 5.5V, (Note 2) E = 1MHz VCC = 5.5V, E = VCC-0.3V, IO = 0mA GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN MAX 0.4 UNITS V
Output High Voltage
VOH
1, 2, 3
2.4
-
V A A A
Input Leakage Current
II
1, 2, 3
-1.0
+1.0
Input/Output Leakage Current Data Retention Supply Current
IIOZ
1, 2, 3
-1.0
+1.0
ICCDR
1, 2, 3
-
25
Operating Supply Current Standby Supply Current
ICCOP
1, 2, 3
-55oC TA +125oC -55oC TA +125oC
-
7
mA A
ICCSB
1, 2, 3
-
50
NOTES: 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP.
153
HM-6514/883
TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested LIMITS GROUP A SUBGROUPS 9, 10, 11 HM-6514S/883 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN MAX 120 HM-6514B/883 MIN MAX 200
HM-6514/883
MIN MAX 300 UNITS ns
PARAMETER Chip Enable Access Time Address Access Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time Write Enable Pulse Width Write Enable Pulse Setup Time Write Enable Pulse Hold Time Data Setup Time
SYMBOL
(NOTES 1, 2) CONDITIONS VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V, Note 3 VCC = 4.5 and 5.5V
(1) TELQV (2) TAVQV (5) TELEH
9, 10, 11
-
120
-
220
-
320
ns
9, 10, 11
120
-
200
-
300
-
ns
(6) TEHEL
VCC = 4.5 and 5.5V
9, 10, 11
50
-
90
-
120
-
ns
(7) TAVEL (8) TELAX (9) TWLWH (10) TWLEH
VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V
9, 10, 11
0
-
20
-
20
-
ns
9, 10, 11
40
-
50
-
50
-
ns
9, 10, 11
120
-
200
-
300
-
ns
9, 10, 11
120
-
200
-
300
-
ns
(11) TELWH (12) TDVWH (13) TWHDX (14) TWLDV (15) TWLEL (16) TEHWH (17) TELEL
VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V
9, 10, 11
120
-
200
-
300
-
ns
9, 10, 11
50
-
120
-
200
-
ns
Data Hold Time
9, 10, 11
0
-
0
-
0
-
ns
Write Data Delay Time Early Output High-Z Time Late Output High-Z Time Read or Write Cycle Time
9, 10, 11
70
-
80
-
100
-
ns
9, 10, 11
0
-
0
-
0
-
ns
9, 10, 11
0
-
0
-
0
-
ns
9, 10, 11
170
-
290
-
420
-
ns
NOTES:
1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL.
154
HM-6514/883
TABLE 3. HM-6514/883 ELECTRICAL PERFORMANCE SPECIFICATIONS HM-6514/883 LIMITS PARAMETER Input Capacitance SYMBOL CI CONDITIONS VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground
VCC = 4.5 and 5.5V
NOTE 1
TEMPERATURE TA = +25oC
MIN -
MAX 8
UNITS pF
Input/Output Capacitance
CIO
1
TA = +25oC
-
10
pF
Chip Enable Output Disable Time Chip Enable Output Disable Time
TELQX
1
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
5
-
TEHQZ
VCC = 4.5 and 5.5V HM-6514S/883 VCC = 4.5 and 5.5V HM-6514B/883 VCC = 4.5 and 5.5V HM-6514/883
1
-
50
ns
1
-
80
ns
1
-
100
ns
High Level Output Voltage NOTES:
VOH2
VCC = 4.5V, IO = -100A
1
VCC -0.4
-
V
1. The parameters listed in Table 3 are controlled via design, or process parameters are characterized upon initial design and after major process and/or design changes. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
155
HM-6514/883 Timing Waveforms
(2) TAVQV (7) TAVEL A (6) TEHEL E (1) TELQV DQ W TIME REFERENCE -1 0 1 2 3 4 5 HIGH Z (3) TELQX (4) TEHQZ VALID DATA OUT HIGH Z (8) TELAX VALID ADD (2) TAVQY (5) TELEH (17) TELEL (7) TAVEL NEXT ADD (6) TEHEL
FIGURE 1. READ CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L E H W X H H H H X H A X V X X X X V DATA I/O DQ Z Z X V V Z Z Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid Read Accomplished Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION
The address information is latched in the on-chip registers on the falling edge of E (T = 0). Minimum address set up and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1) the output becomes
enabled but data is not valid until during time (T = 2). W must remain high throughout the read cycle. After the output data has been read, E may return high (T = 3). This will disable the output buffer and all inputs, and ready the RAM for the next memory cycle (T = 4).
156
HM-6514/883 Timing Waveforms (Continued)
TELAX TAVEL A VALID ADD TELEL TEHEL E TWLEH TELWL TWLWH W HIGH Z DQ TWLDV VALID DATA INPUT TDVWH TELWH TIME REFERENCE -1 0 1 2 3 4 5 TWHDZ HIGH Z TWHEH TELEH TEHEL TEVEL NEXT ADD
FIGURE 2. WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L H X X E H W X X L A X V X X X X V DQ Z Z Z V Z Z Z Memory Disabled Cycle Begins, Addresses are Latched Write Period Begins Data In is Written Write Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION
The write cycle is initiated by the falling edge of E (T = 0), which latches the address information in the on-chip registers. There are two basic types of write cycles, which differ in the control of the common data-in/data-out bus. Case 1: E falls before W falls The output buffers may become enabled (reading) if E falls before W falls. W is used to disable (three-state) the outputs so input data can be applied. TWLDV must be met to allow the W signal time to disable the outputs before applying input data. Also, at the end of the cycle the outputs may become active if W rises before E. The RAM outputs and all inputs will three-state after E rises (TEHQZ). In this type of write cycle TWLEL and TEHWH may be ignored. Case 2: E falls equal to or after W falls, and E rises before or equal to W rising
This E and W control timing will guarantee that the data outputs will stay disabled throughout the cycle, thus simplifying the data input timing. TWLEL and TEHWH must be met, but TWLDV becomes meaningless and can be ignored. In this cycle TDVWH and TWHDX become TDVEH and TEHDX. In other words, reference data setup and hold times to the E rising edge.
IF Case 1 Case 2 E falls before W E falls after W and E rises before W OBSERVE TWLDV TWLEL TEHWH IGNORE TWLEL TWLDV TWHDX
If a series of consecutive write cycles are to be performed, W may be held low until all desired locations have been written (an extension of Case 2).
157
HM-6514/883 Test Load Circuit
DUT (NOTE 1) CL
IOH
+ -
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE: 1. Test head capacitance.
Burn-In Circuit
HM6514/883 CERDIP
VCC F9 F8 F7 F6 F3 F4 F5 F0 1 2 3 4 5 6 7 8 9 A6 A5 A4 A3 A0 A1 A2 E GND VCC 18 A7 17 A8 16 A9 15 DQ0 14 DQ1 13 DQ2 12 DQ3 11 W 10 F1 F2 F10 F11 F12 C1
NOTES: All resistors 47k 5%. F0 = 100kHz 10%. F1 = F0 / 2, F2 = F1 / 2, F3 = F2 / 2 . . . F12 = F11 / 2. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C1 = 0.01F Min.
158
HM-6514/883 Die Characteristics
DIE DIMENSIONS: 136 x 167 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.79 x 105 A/cm 2 LEAD TEMPERATURE (10s soldering): 300oC
Metallization Mask Layout
HM-6514/883
A5 A4 A3 A6 VCC A7 A8 A9
A0 A1
DQ0 DQ1 DQ2
A2 E GND W DQ3
NOTE: 1. Pin numbers correspond to DIP Package only.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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159

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